IBM announced the creation of a 5-nm chip (3 photos + video)
IBM continues to develop a strategy for reducing the size of transistors. It is expected that in 2019, their length will be reduced to 7 nm, and by 2023 the parameter reaches 5 nm. At the moment this figure is produced by the electronics is 10-14 nm. Improving the dimensions will be placed on a single chip the size of a fingernail, not 20, but 30 billion of transistors, thereby increasing the power of any equipment twice. At the request of the developer, a 5 nm solution of 40% more efficient than the existing market 10-nm chips and power consumption is lower by 75% at the same performance. The development is conducted jointly with the Corporation by Samsung and GlobalFoundries.
The last six years, IBM uses the FinFET architecture. In this case, each transistor gets three conductive layers. Now the task will be to handle silicon nanoplates, which are created by the method of UV lithography. With the change of the base due to the increasing number of outlets: they will be four.
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